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16 - bit, 2.5 msps, pulsar 1 5.5 mw adc in lfcsp ad7985 rev. a information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. s pecifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2009 - 2010 analog devices, inc. all rights reserved. features 16- bit resolution with no missing codes throughput: 2.5 msps ( turbo high ) , 2. 0 msps ( turbo low ) low power dissipation 1 5.5 mw at 2.5 msps , with external reference 2 8 mw at 2.5 msps , with internal reference inl: 0.7 lsb typical , 1.5 lsb maximum s nr 88.5 db, with on - chip reference 90 db, with external reference 4.096 v internal reference: typ ical drift of 10 ppm/c pseudo differential analog input voltage range 0 v to v ref with v ref up to 5.0 v a llows use of a ny input range no pipeline delay logic i nterface : 1.8 v/2.5 v/2.7 v serial interface : spi - /qspi? - /microwire? - /dsp - compatible ability to d aisy - chain multiple adcs with busy indicator 2 0 - lead , 4 mm 4 mm lfcsp (qfn) applications battery - powered equipment communications ate data acquisition syst ems medical instruments application diagram 0v to v ref notes 1. gnd refers to refgnd, agnd, and dgnd. ad7985 gnd ref avdd, dvdd vio bvdd 5v 2.5v 1.8v to 2.7v vio sdi sck sdo cnv 3- or 4-wire interface: spi, cs, daisy chain (turbo = low) turbo 10f in+ in? 07947-001 figure 1. general description the ad7985 is a 16- bit , 2.5 msps successive approximation analog - to - digital converter ( sar adc). it contains a low power, high speed, 16- bit sampling adc , an internal conversion clock, an internal reference (and buffer), error correction circuits, and a versatile serial interface port. on the rising edge of c n v, t h e ad7985 samples an analog input , in+ , between 0 v and ref with respect to a ground sense, in ?. the ad7985 features a very high sampling rate turbo mode ( turbo is high ) and a reduced power normal mode ( turbo is low ) for low power applications where the power is scaled with the throughput. in normal mode ( turbo is low ), t he spi - compatible serial in ter - face also features the ability, using the sdi input, to daisy - chain several adcs on a single 3 - wire bus and provide an optional busy indicator. it is compatible with 1.8 v, 2.5 v, and 2.7 v supplies using the separate vio supply. the ad7985 is availabl e in a 2 0 - lead lfcsp with operation specified from ? 40c to +85 c. table 1 . msop, lfcsp , 14- /16 - /18- bit pulsar? adcs 1 type 100 ksps 250 ksps 400 ksps to 500 ksps 1000 ksps adc driver 14- bit ad7940 ad7942 2 ad7946 2 16- bit ad7680 ad7685 2 ad7686 2 ad7980 2 ad a4941 -1 ad7683 ad7687 2 ad7688 2 ad7983 2 ada4841 -x ad7684 ad769 4 ad7693 2 ad7985 3 ad8021 18- bit ad7691 2 ad7690 2 ad7982 2 ada49 41 -1 ad7984 2 ada4841 -x ad79 86 3 ad8021 1 see www.analog.com for the latest selection of pulsar adcs and adc drivers. 2 pin - for - pin compatible with all other parts marked with this endnote . 3 the ad7985 and ad7986 are pin - for - pin compatible.
ad7985 rev. a | page 2 of 28 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 application diagram ........................................................................ 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 timing specifications .................................................................. 5 absolute maximum ratings ............................................................ 6 esd caution .................................................................................. 6 pin configuration and function descriptions ............................. 7 typical performance chara cteristics ............................................. 9 terminology .................................................................................... 12 theory of operation ...................................................................... 13 circuit infor mation .................................................................... 13 converter operation .................................................................. 13 conversion modes of operation .............................................. 13 typical connection diagram .................................................... 14 analog inputs .............................................................................. 15 driver amplifier choice ........................................................... 15 voltage reference input ............................................................ 16 power supply ............................................................................... 16 digital interface .............................................................................. 17 data reading options ............................................................... 18 cs mode, 3 - wire without busy indicator ............................. 19 cs m ode, 3 - wire with busy indicator .................................... 20 cs mode, 4 - wire without busy indicator ............................. 21 cs mo de, 4 - wire with busy indicator .................................... 22 chain mode without busy indicator ...................................... 23 chain mode with busy indicator ............................................. 24 applications information .............................................................. 25 layout .......................................................................................... 25 evaluating ad7985 performance ............................................. 25 outline dimensions ....................................................................... 27 ordering guide .......................................................................... 27 revision history 8/10 rev. 0 to rev. a change to table 4, conversion t ime: cnv rising edge to data available ............................................................................... 5 9 /09 revision 0: initial version
ad7985 rev. a | page 3 of 28 specifications av dd = dvdd = 2.5 v, bvdd = 5 v, vio = 1.8 v to 2.7 v, v ref = 4.096 v, t a = ? 40c to +85c, unless otherwise noted. table 2 . parameter test c onditions /comments min typ max unit resolution 16 bits analog input voltage range ( in+ ) ? ( in ? ) 0 v ref v absolute input voltage in+ ?0.1 v ref + 0.1 v in ? ?0.1 + 0.1 v leakage current at 25c acquisition phase 250 na input impedance see the analog inputs section accuracy no missing codes 16 bits differential nonl inearity error , dnl ?0.9 9 0. 5 0 + 0.9 9 lsb 1 integral nonl inearity error , inl ? 1 .50 0. 7 + 1 .50 lsb 1 transition noise 0.8 lsb 1 gain error, t min to t max 2 ? 15 2 + 15 lsb 1 gain error temperature drift 0. 8 ppm/c zero error, t min to t max 2 ?0.9 9 0. 08 +0.9 9 mv zero temperature drift 0.55 ppm/c power supply sensitivity avdd = 2.5 v 5% 90 db 3 throughput conversion rate 0 2. 5 msps transient response full - scal e step 100 ns ac accuracy dynamic range v ref = 4.096 v, internal reference 87. 5 89 db 3 v ref = 5.0 v, external reference 89. 0 9 0 db 3 signal -to - noise ra tio, snr f in = 20 khz, v ref = 4.096 v, internal reference 87. 0 88. 5 db 3 f in = 20 khz, v ref = 5.0 v, external reference 89. 0 9 0 . 0 db 3 spurious - free dynamic rang e, sfdr f in = 20 khz 103 db 3 total harmonic distortion 4 , thd f in = 20 khz, v ref = 4.096 v, internal reference ?1 00 db 3 signal -to - noise - and - distortion ratio , s inad f in = 20 khz, v ref = 4.096 v 9 0 .5 db 3 sampling dynamics ?3 db input bandwidth 19 mhz aperture delay 0.7 ns 1 lsb means least significant bit. with the 4.096 v input range, one lsb is 62.5 v. 2 see the terminology section. the se specifications include full temperature range variation but not the error contribution from the external reference. 3 all specifications expressed in decibels are referred to a full - scale input fs r and t ested with an input signal at 0.5 db below full sc ale, unless otherwise specified . 4 tested fully in production at f in = 1 khz.
ad7985 rev. a | page 4 of 28 table 3 . parameter test conditions /comments min typ ma x unit internal reference pdref is low output voltage t a = 25c 4.081 4.096 4.111 v temperature drift ?40c to +85c 10 ppm/c line regulation avdd = 2.5 v 5% 5 0 ppm/v turn - on settling time c ref = 10 f, c refin = 0.1 f 4 0 ms refin outp ut voltage refin at 25c 1.2 v refin output resistance 6 k ? external reference pdref is high , refin is low voltage range 2.4 5.1 v current drain 500 a reference buffer refin input voltage range 1.2 v refin input current 160 a digital inputs logic levels v il ?0.3 0.1 vio v v ih 0.9 vio vio + 0.3 v i il ? 1 + 1 a i ih ? 1 + 1 a digital outputs data format serial 16 bits, straight binary pipeline delay conversion results available immediately after completed conversion v ol i sink = +500 a 0.4 v v oh i source = ?500 a vio ? 0.3 v power supplies avdd, dvdd 2.375 2.5 2.625 v bvdd 4.75 5.0 5.25 v vio specified performance 1.8 2.5 2.7 v standby current 1 , 2 avdd = dvdd = vio = 2.5 v 1.0 a power dissipation with internal reference 2.5 msps throughput 28 33 mw 2.0 msps throughput 25 30 mw with ex ternal reference 2 .5 msps throughput 1 5.5 17 mw 2.0 msps throughput 12 13 mw temperature range 3 specified performanc e t min to t max ?40 +85 c 1 with all digital inputs forced to vio or gnd as required. 2 during acquisition phase. 3 contact an analog devices, inc., sales representative for the extended temperature range.
ad7985 rev. a | page 5 of 28 timing specification s avdd = dvdd = 2.5 v, bvdd = 5 v, vio = 1.8 v to 2.7 v, v ref = 4.096 v, t a = ?40c to +85c, unless otherwise noted. 1 table 4 . parameter symbol test conditions/comments min typ max unit conver sion time: cnv rising edge to data available t conv turbo m ode/ n ormal m ode 320/ 42 0 ns acquisition time t acq 8 0 ns time between conversions t cyc turbo m ode/ n ormal m ode 4 00/ 50 0 ns cnv pulse width t cnvh cs m ode 10 ns data r ead during conversion t data turbo m ode/ n ormal m ode 190/29 0 ns quiet time during acquisition from last sck falling edge to cnv rising edge t quiet 20 ns sck period t sck cs m ode 9 ns t sck chain m ode 11 ns sck low time t sck l 3.5 ns sck high time t sckh 3.5 ns sck falling edge to data remains valid t hsdo 2 ns sck falling edge to data valid delay t dsdo 4 ns cnv or sdi low to sdo d1 5 msb valid t en 5 ns cnv or sdi high or last sck falling edge to sdo high imp edance t dis cs m ode 8 ns sdi valid setup time from cnv rising edge t ssdicnv 4 ns sdi valid hold time from cnv rising edge t hsdicnv cs m ode 0 ns t hsdicnv chain m ode 0 ns sck valid setup time from c nv rising edge t ssckcnv chain m ode 5 ns sck valid hold time from cnv rising edge t hsckcnv chain m ode 5 ns sdi valid setup time from sck falling edge t ssdisck chain m ode 2 ns sdi valid hold time from sck falling edge t hsdisck chain m ode 3 ns sdi high to sdo high t dsdosdi chain m ode with b usy i ndicator 1 5 ns 1 see figure 2 and figure 3 for load conditions. 500a i ol 500a i oh 1.4v to sdo c l 20pf 07947-002 figure 2 . load circuit for digital interface timing 90% vio 10% vio v ih 1 v il 1 v il 1 v ih 1 t delay t delay 1 minimum v ih and maximum v il used. see digital inputs specifications in table 3. 07947-003 figure 3 . voltage levels for timing
ad7985 rev. a | page 6 of 28 absolute maximum rat ings table 5 . parameter rating analog inputs in+, in ? to gnd 1 ?0.3 v to v ref + 0.3 v or 130 ma supply voltage ref, bvdd to gnd , refgnd ?0.3 v to +6.0 v a vdd , dvdd , vio to gnd ?0.3 v to +2.7 v a vdd , dvdd to vio ?6 v to +3 v digital inputs to gnd ?0.3 v to vio + 0.3 v digital outputs to gnd ?0.3 v to vio + 0.3 v storage temperature range ?65c to +150c junction temperature 150c ja thermal impedance 2 0 - lead lfcsp ( qfn) 30.4 c/w lead temperatures vapor phase (60 sec) 215c infrare d (1 5 sec) 220c 1 see the analog inputs section for an explanation of in+ and in ?. stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operation al section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. esd caution
ad7985 rev. a | page 7 of 28 pin configuration an d function descripti ons pin 1 indic a t or 1 ref 2 ref 3 refgnd 4 refgnd 5 in? 13 cnv 14 sdi 15 turbo 12 sck 1 1 dvdd 6 in+ 7 pdref 8 vio 10 dgnd 9 sdo 18 agnd 19 bvdd 20 refin 17 agnd 16 a vdd t op view (not to scale) ad7985 notes 1. the exposed pad is not connected internally. for increased reliability of the solder joints, it is recommended that the pad be soldered to the system ground plane. 07947-004 figure 4 . pin configuration table 6 . pin function descriptions pin no. mnemonic type 1 description 1, 2 ref ai reference output/ input voltage. when pdref is low , the internal reference and buffer are enabled , producing 4.096 v on this pin. when pdref is high , the internal reference and buffer are disabled, allowing an externally supplied voltage reference up to 5.0 v. decoupling is required with or without the internal reference and buffer. this pin is referred to the refgnd pins a nd should be decoupled closely to the refgnd pins with a 10 f capacitor. 3, 4 refgnd ai reference input analog ground. 5 in ? ai analog input ground sense. connect this pin to the analog ground plane or to a remote ground sense . 6 in + ai analog input. this pin is referred to in ?. the voltage range, that is, the difference between in+ and in?, is 0 v to v ref . 7 pdref di internal reference power - down input. when this pin is low, the internal reference is enabled. when this pin is high, the internal refe rence is powered down and an external reference must be used. 8 vio p input/output interface digital power. nominally at the same supply voltage as the host interface (1.8 v, 2.5 v, or 2.7 v). 9 sdo do serial data output. the conversion result is output on this pin. it is synchronized to sck. 10 dgnd p digital power ground. 11 dvdd p digital power. nominally at 2.5 v. 12 sck di serial data clock input. when the part is selected, the conversion result is shifted out by this clock. 13 cnv di conver t i nput. this input has multiple functions. on its leading edge, it initiates the conversions and selects the interface mode of the part: chain mode or cs mode. in cs mode, the sdo pin is enabled when cnv is low. in chain mode, the data should be read when cnv is high. 14 sdi di serial data input. this input has multiple functions. it selects the inter face mode of the adc as follows. chain mode is selected if sdi is low during the cnv rising edge. in chain mode , sdi is used as a data input to daisy - chain the conversion results of two or more adcs onto a single sdo line. the digital data level on sdi is output on sdo with a delay of 1 6 sck cycles. cs mode is selected if sdi is high during t he cnv rising edge. in cs mode, either sdi or cnv can enable the serial output signals when low. if sdi or cnv is low when the conversion is complete, the busy indicator feature is enabled. 15 turbo di conversion mode selection. whe n turbo is high , the maximum throughput ( 2.5 msps ) is achieved , and t he adc does not power down between conversions. when turbo is low , the maximum throughput is lower ( 2.0 msps) , and t he adc powers down between conversions. 16 avdd p input analog power. nominally at 2.5 v. 17, 18 agnd p analog power ground.
ad7985 rev. a | page 8 of 28 pin no. mnemonic type 1 description 19 bvdd p reference b uffer p ower. nominally at 5 .0 v . if an external reference buffer is used to achieve the maximum snr performance with a 5 v reference, the reference buffer must be powered down by connecting the refin pin to ground. the external reference buffer must be connected to the bvdd pin . 20 refin ai/o internal reference output/reference buffer input. when pdref is low , the internal band gap reference produces a 1.2 v (typical) voltage on this pin, which needs external decoupling (0.1 f typical). when pdref is high , use an external reference to provide 1.2 v (typical) to this pin. when pdref is high and refin is low , the on - chip reference buffer and the band gap reference are powered down. an external reference must be connected to ref and bvdd. 21 exposed pad ep the exposed pad is not connected internally. for increased reliability of the solder joints, it is recommended that the pad be soldered to the system ground plane. 1 ai = analog input , ai/o = bidirectional analog, di = digital input, do = digital output, and p = power .
ad7985 rev. a | page 9 of 28 typical pe rformance characteri stics avdd = dvdd = vio = 2.5 v, bvdd = 5.0 v, v ref = 5.0 v , e xternal r eference (pdref is h igh, refin is low), unless otherwise noted. 1.25 ?1.25 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 1.00 0 16,384 32,768 49,152 65,536 inl (lsb) code positive inl = +0.38lsb negative inl = ?0.46lsb 07947-105 figure 5 . integral nonlinearity vs. code 60,000 50,000 40,000 30,000 20,000 10,000 0 counts code in hex 7ffc 7ffd 7ffe 7fff 8000 8001 8002 8003 8004 0 122 6150 38,843 57,138 26,249 2537 33 0 07947-106 figure 6. histogram of dc input at code center (external reference) 60,000 50,000 40,000 30,000 20,000 10,000 0 counts code in hex 7ffd 7ffc 7ffb 7ffe 7fff 8000 8001 8002 8003 8004 8005 0 11 565 33,064 49,585 31,957 7024 403 8 0 8455 07947-107 figure 7. histogram of dc input at code center (internal reference) 1.00 ?1.00 ?0.75 ?0.50 ?0.25 0 0.25 0.50 0.75 0 16,384 32,768 49,152 65,536 dnl (lsb) code positive dnl = +0.19lsb negative dnl = ?0.20lsb 07947-108 figure 8 . differential nonlinearity vs. code 60,000 50,000 40,000 30,000 20,000 10,000 0 counts code in hex 7ffd 7ffc 7ffb 7ffe 7fff 8000 8001 8002 8003 8004 0 2 479 11,888 48,730 53,522 15,645 800 6 0 07947-109 figure 9. histogram of dc input at code transition (external reference) 50,000 45,000 40,000 35,000 30,000 25,000 20,000 15,000 10,000 5000 0 counts code in hex 7ffe 7ffd 7ffc 7fff 8000 8001 8002 8003 8004 8005 0 90 2947 20,474 46,649 43,622 15,598 1662 30 0 07947-110 figure 10 . histogram of dc input at code transition (internal reference)
ad7985 rev. a | page 10 of 28 0 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 1250 1000 750 500 250 amplitude (db) frequency (khz) f s = 2.5msps f in = 20khz snr = 89.87db thd = ?102.76db sinad = 89.66db 07947-111 figure 11 . fft plot (external reference) 100 95 90 85 80 16 15 14 13 12 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 snr, sinad (db) enob (bits) reference voltage (v) snr sinad enob 07947-112 figure 12 . snr, sinad, and enob vs. reference voltage 95 90 85 80 75 70 65 1 1000 100 10 sinad (db) frequency (khz) 07947-113 figure 13 . sinad vs. frequency 0 ?180 ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 1250 1000 750 500 250 amplitude (db) frequency (khz) f s = 2.5msps f in = 20khz snr = 88.45db thd = ?103.42db sinad = 88.32db 07947-114 figure 14 . fft plot (internal reference) ?90 ?95 ?100 ?105 ?110 100 95 90 85 80 2.50 2.75 3.00 3.25 3.50 3.75 4.00 4.25 4.50 4.75 5.00 thd (db) sfdr (db) reference voltage (v) sfdr thd 07947-115 figure 15 . thd and sfdr vs. reference voltage ?85 ?90 ?95 ?100 ?105 ?110 1 1000 100 10 thd (db) frequency (khz) 07947-116 figure 16 . thd vs. frequency
ad7985 rev. a | page 11 of 28 95 94 93 92 91 90 89 88 87 86 85 ?10 ?9 ?8 ?7 ?6 ?5 ?4 ?3 ?2 ?1 0 snr (db) input level (dbfs) 07947-117 figure 17 . snr v s. input level 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 2.375 2.625 i avdd i dvdd i vio i bvdd i ref 2.575 2.525 2.475 2.425 operating current (ma) avdd and dvdd voltage (v) 07947-118 figure 18 . operating current vs. supply voltage 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 ?55 ?35 ?15 5 25 45 65 85 105 125 i avdd i bvdd i ref operating current (ma) temperature (c) 07947-119 figure 19 . operating current v s. temperature 14 12 10 8 6 4 2 0 ?55 ?35 ?15 5 25 45 65 85 105 125 supply current (a) temperature (c) i avdd + i dvdd + i vio 07947-120 figure 20 . power - down current vs. temperature
ad7985 rev. a | page 12 of 28 terminology aperture delay aperture delay is the measure of the acquisition performance and is the time between the rising edge of the cnv input and when the input signal is held for a conversion. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. dnl is the maximum deviation from this ideal value. it is often specified in terms of resolution for whi ch no missing codes are guaranteed. dynamic range dynamic range is the ratio of the rms value of the full scale to the total rms noise measured with the inputs shorted together. the value for dynamic range is expressed in decibels. it is mea - sured with a s ign al at ?60 dbf s so that it includes all noise sources and dnl artifacts. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is expressed in bits and is related to sinad as follows: enob = ( sinad db ? 1.76)/6.02 effective resolution effective resolution is expressed in bits and is calculated as follows: effective resolution = log 2 (2 n / rms input noise ) gain error the last transition (from 111 10 to 111 1 1) should occur for an analog voltage 1 ? lsb below the nom inal full scale ( 4. 999886 v for the 0 v to 5 v range). the gain error is the deviation of the difference between the actual level of the last transition and the actual level of the first transition from the difference between the ideal levels. integral non linearity error (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs ? lsb before the first code transition. positive full scale is de fined as a level 1? lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line (see figure 22). noise - free code resolution noise - free code resolution i s the number of bits beyond which it is impossible to distinctly resolve individual codes. it is expressed in bits and is calculated as follows: noise - free code resolution = log 2 (2 n / peak - to - peak noise ) signal -to - noise ratio (snr) snr is the ratio of the rm s value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal -to - noise - and - distortion ratio (sinad) sinad is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for sinad is expressed in decibels. spurious - free dynamic range (sfdr) sfdr is the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full - scale input signal and is expres sed in decibels. transient response transient response is the time required for the adc to accurately acquire its input after a full - scale step function is applied. zero error zero error is the difference between the ideal midscale voltage, that is, 0 v, f rom the actual voltage producing the midscale output code, that is, 0 lsb.
ad7985 rev. a | page 13 of 28 th e ory of operation comp switches control busy output code cnv control logic sw+ lsb sw? lsb in+ ref refgnd in? msb msb c c 4c 2c 16,384c 32,768c c c 4c 2c 16,384c 32,768c 07947-005 figure 21 . adc simplified schematic circuit information the ad7985 is a fast, low power, single - supply, precise , 16- bit adc using a successive approximation architecture . the ad7985 features different modes to optimize performance according to the application. in turbo mode, the ad7985 is capable of convert ing 2,5 00,000 samples per second ( 2.5 msps ). the ad7985 provides the user wit h an on - chip track - and - hold and does not exhibit any pipeline delay or latency, making it ideal for multiple multiplexed channel applications. the ad7985 can be interfaced to any 1.8 v to 2.7 v digital logic family. it is available in a space - saving 2 0 - le ad lfcsp that allows flexible configurations. it is pin - for - pin compatible with the 18- bit ad7986. converter operation the ad7985 is a successive appr oximation adc based on a charge redistribution dac. figure 21 sh ows the simplified schematic of the adc. the capacitive dac consists of two identical arrays of 1 6 binary - weighted capacitors that are connected to the two comparator inputs. during the acquisition phase, t he t erminals of the array tied to the input of the comparator are connected to a gnd via sw+ and sw ? . all independent switches are connected to the analog inputs. th erefore , the capacitor arrays are used as sampling capacitors and acquire the analog signal on the in+ and in ? inputs. when the acquisition ph ase is complete d and the cnv input goes high, a conversion phase is initiated. when the conversion phase begins, sw+ and sw ? are opened first. the two capacitor arrays are then disconnected from the analog inputs and connected to the ref gnd input. therefor e, the differential voltage between the in+ and in ? inputs captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbalanced. by switch - ing each element of the capacitor array between ref gnd and r ef, the comparator input varies by binary - weighted voltage steps (v ref /2, v ref /4 , v ref / 65, 536 ). the control logic toggles these switches, starting with the msb, to bring the comparator back into a balanced condition. after the completion of this process, the part returns to the acquisition phase , and the control logic generates the adc output code and a busy signal indicator. because the ad7985 has an on - board conversion clock, the serial clock, sck, is not required for the conversion process. c onversion modes of operation the ad7985 features two conversion modes of operation : turbo and normal. turbo conversion mode (turbo is high ) allow s the fastest conversion rate of up to 2.5 msps and does not power down between conversions. the first conversion in t urb o mode should be ignored because it contai ns meaningless data. for applica tions that require lower power and slightly slower sampling rates, the n ormal mode ( turbo is low ) allows a maximum conversion rate of 2 .0 msps and powers down between conversion s. t he first conversion in normal mode contain s meaningful data.
ad7985 rev. a | page 14 of 28 transfer functions the ideal transfer characteristic for the ad7985 is shown in figure 22 and table 7 . 000 ... 00 0 000 ... 00 1 000 ... 01 0 adc code (straight binary) ana l og i n pu t +f sr ? 1 . 5 l sb +f sr ? 1 l sb ? f sr + 1 l sb ? f sr ? f sr + 0 . 5 l sb 07947-006 11 1 ... 101 11 1 ... 1 10 11 1 ... 11 1 figure 22 . adc ideal transfer function table 7 . output codes and ideal input voltages description analog input , v ref 4.096 v digital output code (he) fsr C 1 lsb 4.095938 v 0x ffff 1 midscale + 1 lsb 2 .048063 v 0x 8001 midscale 2.048 v 0x 8000 midscale C 1 lsb 2.047938 v 0x 7fff C fsr + 1 lsb 62.5 v 0 x0 001 C fsr 0 v 0 x0 000 2 1 this is also the code for an overranged analog input (v in+ ? v in ? above v ref ? ref gnd). 2 this is also the code for an underran ged analog input (v in+ ? v in ? below ref gnd). typical connection d iagram figure 23 shows an example of the recommended connection diagram for the ad7985 when multiple supplies are available. 07947-007 notes 1. gnd refers to refgnd, agnd, and dgnd. ad7985 gnd ref avdd, dvdd vio bvdd 5v 2.5v 1.8v to 2.7v vio sdi sck sdo cnv 3- or 4-wire interface: spi, cs, daisy chain (turbo = low) turbo 10f in+ in? 2.7nf 15? v? 0v to v ref v+ figure 23 . typical application diagram with multiple supplies
ad7985 rev. a | page 15 of 28 analog input s figure 24 shows an equivalent circuit of the input structure of the ad7985 . the two diodes, d1 and d2, provide esd protectio n for the analog inputs , i n+ and in ?. care must be taken to ensure that the analog input signal does not exceed the reference input voltage (ref) by more than 0.3 v . if the analog input signal exceeds this level, the diodes be come forward - bias ed and start conducting current. these diodes can handle a forward - biased current of 130 ma maximum. however, if the supplies of the input buffer (for example, the v+ and v ? supplies of the buffer amplifier in figure 23) are different from those of r ef , the analog input signal may eventually exceed the supply rails by more than 0.3 v. in such a case (for example, an input buffer with a short circuit ) , the current limitation can be used to protect the part. c pin ref r in c in d1 d2 in+ or in? refgnd 07947-008 figure 24 . equival ent analog input circuit the analog input structure allows the sampling of the true differential signal between in+ and in ?. by using these differential inputs, signals common to both inputs are rejected. during the acquisition phase, the impedance of the analog inputs (in+ and i n ?) can be modeled as a parallel combination of capacitor c pin and the network formed by the series connection of r in and c in . c pin is primarily the pin capacitance. r in is typically 400 ? and is a lumped component composed of serial resistors and the on r esistance of the switches. c in is typically 30 pf and is mainly the adc sampling capacitor. during the sampling phase, where the switches are close d, the input impedance is limited to c pin . r in and c in make a one - pole, low - pass filter that reduces undesir able aliasing effects and limits noise. when the source impedance of the driving circuit is low, the ad7985 can be driven directly. large source impedances significantly affect the ac performance, especially thd. the dc performances are less sensitive to the input impedance. the maximum source impedance depends on the amount of thd that can be tolerated. the thd degrades as a function of the source impedance and the maximum input frequency. driver amplifier cho ice although the ad7985 is easy to drive, the driver amplifier must meet the following requirements: ? the noise generated by the driver amplifier must be kept as low as possible to preserve the snr and transition noise performance of the ad7985 . the noise from the driver is filtered by the ad7985 anal og input circuit s one - pole, low - pass filter , made by r in and c in , or by the external filter, if one is used. because the typical noise of the ad7985 is 5 0 v rms, the snr degradation due to the amplifier is ? ? ? ? ? ? ? ? ? ? ? ? + = ? 2 2 ) ( 2 50 50 log 20 n 3db loss ne f snr where: f C 3db is the inpu t bandwidth , in megahertz, of the ad7985 ( 2 0 mhz) or the cutoff frequency of the input filter, if one is used. n is the noise gain of the amplifier (for examp le, 1 in buffer configuration). e n is the equivalent input noise voltage of the op am p, in nv/ hz. ? for ac applications, the driver should have a thd perfor - mance commensurate with that of the ad7985 . ? for multichannel multiplexed applications, the driver amplifier and the ad7985 analog input circuit must settle for a full - scale step onto th e capacitor array at a 16 - bit level (0.0015 %, 15 ppm). in the data sheet of the driver amplifier , settling at 0.1% to 0.01% is more commonly specified. this value may differ significantly from the settling time at a 16- bit level and should be verified pri or to driver selection. table 8 . recommended driver amplifiers amplifier typical application ad8021 very low noise and high frequency ad8022 low noise and high frequency ada4899 -1 ultralow noise and high frequency ad8014 low power and high frequency
ad7985 rev. a | page 16 of 28 voltage reference in put the ad7985 allows the choice of a very low temperature drift internal voltage reference, an external reference, or an external buffered reference. t h e internal reference of the ad7985 provides excellent performance and can be used in almost all applications. internal referenc e , ref = 4.096 v (pdref low) to use the internal reference, the pdref input must be low. this enables the on - chip band gap reference and buffer, result - ing in a 4.096 v reference on the ref pin (1.2 v on refin) . the internal reference is temperature compen sated to 4.096 v 1 5 mv. the reference is trimmed to provide a typical drift of 10 ppm/c. the output resistance of ref in is 6 k ? when the internal reference is enabled. it is necessary to decouple this pin with a ceramic capacitor of at least 100 n f. the output resistance of refin and the decoupling capacitor form an rc filter , which helps to reduce noise. because the outp ut impedance of ref in is typically 6 k ?, relative humidity (among other industrial contamina nts ) can directly affect the drift characteristics of the reference. a guard ring is typically used to reduce the effects of drift under such circumstances . however , the fine pitch of the ad7985 makes this difficult to implement. one solution, in these industrial and other types of applications, is to use a conformal coating, such as dow corning? 1 - 2577 or humiseal? 1b73. external 1.2 v reference and internal buffer (pdref high) to use an external reference along with the internal buffer, pdref must be high. this powers down the internal reference and allows the 1.2 v reference to be applied to refin, producing 4.096 v (typically) on the ref pin. extern al reference (pd ref high, re f in low ) to apply an external r eference voltage directly to the ref pin, pdref should be tied high and re f in should be tied low. bvdd should also be driven to the same potential as ref. for example , if ref = 2.5 v, bvdd should be tied to 2.5 v. the advantages of directly using an external voltage reference are as follows : ? snr and dynamic range improvement (about 1.7 db) resulting from the use of a larger reference voltage (5 v) instead of a typical 4.096 v reference when the internal referen ce is used. this is calculated by ? ? ? ? ? ? = 0 . 5 096 . 4 log 20 snr ? p ower savings when the internal reference is powered down (pdref high). reference decoupling the ad7985 voltage reference input, ref, has a dynamic input impedance that requires careful decoupling b e tween the ref and refgnd pins. the layout section d escribes how this can be done. when using an external reference, a very low impedance source (for example, a reference buffer using the ad8031 or the ad8605 ) and a 10 f (x5r, 0805 size) ceramic chip capacitor are appro - priate for optimum performance. if an unbuffered reference voltage is used, the decoupling value depends on the reference u sed. for example , a 22 f (x5r, 1206 size) ceramic chip capacitor is appropriate for optimum performance using a low temperature drift adr43x reference. if desired, a reference decoupling capacitor with a value as sm all as 2.2 f can be used with minimal impact on performance, especially dnl. in any case , there is no need for an additional lower value ceramic decoupling capacitor (for example, 100 nf) between the ref and ref gnd pins. power supply the ad7985 ha s four power supply pins: a n analog supply ( a vdd ) , a buffer supply (bvdd), a digital supply (dvdd), and a digital input/output interface supply ( vio ) . vio allows direct interface with any logic from 1.8 v to 2.7 v . to reduce the number of supplies needed, vi o , dvdd, and a vdd can be tied together. the power su ppl ies do not need to be started in a par - ticular sequenc e . in ad dition, the ad7985 is very insensitive to power supply variations over a wide frequency range. in normal m ode, the ad7985 powers down autom atically at the end of each conversion phase and, therefore, the power scales li nearly with the sampling rate. this makes the part ideal for low sampling rate s (eve n a few sps) and battery - powered applications. 10 1 0.1 0.01 0.1 1 operating current (ma) sampling rate (msps) 07947-121 i bvdd i avdd i dvdd i vio i vref figure 25 . operat ing current vs. sampling rate in normal mode
ad7985 rev. a | page 17 of 28 digital interface although the ad7985 has a reduced number of pins, it offers flexibility in its serial interface modes. i n cs mode, the ad7985 is compatible with spi, microwire, qspi, and digital hosts. in cs mode, the ad7985 can use either a 3 - wire or a 4 - wire interface. a 3 - wire interface that uses the cnv, sck, and sdo signals minimizes wiring connections , which is useful, for example , in isolated applications. a 4 - wire interface that uses the sdi, cnv, sck, and sdo signals allows cnv, which initiates conversions, to be independent of the readback timing (sdi). this is useful in low jitter sampling or simultaneous sampling applications. in chain mode, the ad7985 provide s a daisy - chain feature that uses the sdi input for cascading multiple adcs on a single data line similar to a shift register. chain mode is available only in n ormal mode ( turbo is low ). the mode in which the part operates depends on the sdi level when the cnv rising edge occurs. cs mode is selected if sdi is high, and chain mode is selected if sdi is low. the sdi hold time is such that when sdi and cnv are connected together, chain mode is always selected. in n ormal mode operation, the ad7985 offers the option of forcing a start bit in front of the data bits. this start bit can be used as a busy signal indicator to interrupt the digital host and trigger the data reading. otherwise, without a busy indicator, the user must time out the maximum conversion time prior to readback. the busy indicator feature is enabled i n cs mode if cnv or sdi is low when the adc conversion ends (see figure 29 and figure 33) . turbo must be kept low for both digital interfaces. when cnv is low, read back can occur during conversion or acquisition, or it can be split across acquisition and conversion , as described in the following sections. a disco ntinuous sck is recommended because the part is selected with cnv low, and sck a ctivity begins to clock out data. note that in the following sections, the timing diagrams indicate digital activity (sck, cnv, sdi, and sdo ) during the conversion. however, du e to the possibility of performance degradation, digi - tal activity should occur only prior to the safe data reading time, t data , because the ad7985 provide s error correction circuitry that can correct for an incorrect bit decision during this time. from t d ata to t conv , there is no error correction , and conve rsion results may be corrupted. similarly, t quiet , the time from the last falling edge of sck to the rising edge of cnv, must remain free of digital activity. the user should configure the ad7985 and in itiate the busy indicator (if desired in normal mode ) prior to t data . it is also possible to corrupt the sample by having sck near the sampling instant. therefore, it is recommended that the digital pins be kept quiet for approximately 2 0 ns before and 10 ns after the rising edge of cnv, using a discontinuous sck whenever possible to avoid any potential performance degradation.
ad7985 rev. a | page 18 of 28 d ata reading options there are three different data reading options for the ad7985 . there is the option to read during conversion , to split the read across acquisition and conversion (see figure 28 and figure 29) , and , in normal mode, to read during acquisition. the desired sck frequency largely determ ine s which reading option to use . reading during conversion, fast host (turbo or normal mode) when reading during conversion (n), conversion results are for the previous (n ? 1) conversion. reading should occur only up to t data and, because this time is l imited, the host must use a fast sck. the required sck frequency is calculated by data sck t edges sck number f _ _ to determine the minimum sck frequency, follow these examples to read data from conversion (n ? 1). for t urbo m ode ( 2.5 msps ): number_sck_edges = 1 6 ; t data = 190 ns f sck = 1 6 / 190 ns = 84. 2 mhz for n ormal m ode ( 2.0 msps ): number_sck_edges = 1 6 ; t data = 290 ns f sck = 1 6 / 290 ns = 55.2 mhz the time between t data and t conv i s an i/o quiet time during which digital activity should not occur, or sensitive bit decisions may be corrupt ed . split - reading , any speed host (turbo or normal mode) to allow for a slower sck , there is the option of a split read , where data access starts at the current acquisition (n) and spans into the conversion (n). conversion results a re for the previous (n ? 1) conversion. similar to reading during conversion, split - reading should occur only up to t data . for the maximum throughput, the only time restriction is that split - reading take place during the t acq (min imum ) + ( t data ? t quiet ) time. the time between the falling edge of sck and cnv rising is an acquisition quiet time, t quiet . to determine how to split the read for a particular sck frequency, follow these examples to read data from conversion (n ? 1) . for t urbo m ode ( 2.5 msps ) : f sck = 70 mhz; t data = 190 ns number_sck_edges = 70 mhz 190 ns = 13.3 thirteen bits are read during conversion (n) , and three bits are read during acquisition (n). for n ormal m ode (2 .0 msps ): f sck = 45 mhz; t data = 290 ns number_sck_edges = 45 mhz 290 ns = 13.05 thirteen bits are read during conversion (n) , and three bits are read during acquisition (n). for slow throughputs, the time restriction is dictated by the throughput required by the user; the host is free to run at any speed. similar to reading during acquisition, data access for slow hosts must take place during the acquisition phase with additional time into the conversion. note that data access spanning conversion requires the cnv pin to be driven high to initiate a new conversion, and data a ccess is not allowed when cnv is high. thus, the host must perform two bursts of data access when using this method. reading during acquisition, any speed host ( turbo or normal mode ) when reading during acquisition (n), conversion results are for the prev ious (n ? 1) conversion. maximum th r oughput is achievable in n ormal mode ( 2.0 msps ) ; however , in t urbo mode, 2.5 msps throughput is not achievable. for the maximum throughput, the only time restriction is that reading take place during the t acq (min imum ) t ime. for slow throughputs, the time restriction is dictated by th e throughput required by the user; the host is free to run at any speed. thus , for slow hosts, data access must take place during the acquisi - tion phase.
ad7985 rev. a | page 19 of 28 cs mode, 3 - wire without busy in dicator this mode is usually used when a single ad7985 is connected to an spi - compatible digital host. the connection diagram is shown in figure 26 , and the corresponding timing is given in figure 27. with sdi tied to vio, a rising edge on cnv initiates a con - version, selects cs mode, and forces sdo to high impedance. when a conversion is initiated, it continues until complet ion , irrespective of the state of cnv. this can be useful, for example , to bring cnv low to select other spi devices, such as analog multiplexers; however, cnv must be returned high before the minimum conversion time elapses and then held high for the max imum possible conversion time to avoid the generation of the busy signal indicator. when the conversion is complete, the ad7985 enters the acquisition phase and powers down. when cnv goes low, the msb is output onto sdo. the remaining data bits are clocke d by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided that it has an acceptable hold time. after th e 1 6 th sck falling edge or when cnv goes high (whichever occurs first), sdo returns to high impedance. ad7985 sdi sdo cnv sck convert data in clk digital host vio 07947-009 figure 26 . cs mode, 3 - wire without busy indicator connection diagram (sdi high) 07947-010 acquisition (n) acquisition (n + 1) acquisition (n ? 1) 1 2 begin data (n ? 1) conversion (n) end data (n ? 1) sck cnv sdo 14 15 conversion (n ? 1) end data (n ? 2) t conv t data 0 (i/o quiet time) (i/o quiet time) 16 14 15 16 1 15 14 13 2 0 1 2 sdi = 1 > t conv (i/o quiet time) t cyc t acq t cnvh t quiet t sck t dis t dis t dis t dis t en t en t dsdo t hsdo t data t conv figure 27 . cs mode, 3 - wire without busy indicator serial interface timing (sdi high)
ad7985 rev. a | page 20 of 28 cs mode, 3 - wire with busy indic ator this mode is usually used when a single ad7985 is connected to an spi - compatibl e digital host that has an interrupt input. it is available only in n ormal conversion mode ( turbo is low). the connection diagram is shown in figure 28, and the corre - sponding timing is given in figure 29 . with sdi tied to vio, a rising edge on cnv initiates a con - version, selects cs mode, and forces sdo to high impedance. sdo is maintained in high impedance until the completion of the conversion , irrespective of the state of cnv. prior to the minimum conversion time, cnv can be used to select other spi devices, such as analog multiplexers, but cnv must be returned low before the minimum conversion time elapses and then held low for the maximum po ssible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high imped - ance to low impedance. with a pull - up on the sdo line, this transition can be used as an interrupt signal to initia te the data read back controlled by the digital host. the ad7985 then enters the acquisition phase and powers down. the data bits are then clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided that it has an acceptable hold time. after the optional 1 7 th sck falling edge , sdo returns to high impedance. if multiple ad7985 device s are selected at the same time, the sdo output pin handles this contention without damage or induced latch - up. meanwhile, it is recommended that this contention be kept as short as possible to limit extra power dissipation. ad7985 sdi sdo cnv sck convert data in clk digital host vio irq vio 47k? turbo 07947-011 figure 28 . cs mode, 3 - wire with busy indicator connection diagram (sdi high) sdo d15 d14 d1 d0 t dis sck 1 2 3 15 16 17 t sck t sckl t sckh t hsdo t dsdo cnv conversion acquisition t conv t cyc acquisition turbo = 0 sdi = 1 t cnvh t acq t quiet (i/o quiet time) 07947-012 figure 29 . cs mode, 3 - wire with busy indicator serial interface timing (sdi high)
ad7985 rev. a | page 21 of 28 cs mod e, 4 - wire without busy in dicator this mode is usually used when multiple ad7985 device s are connected to an spi - compatible digital host. a connection dia - gram example using two ad7985 device s is shown in figure 3 0 , and the corresponding timing is given in figure 31. with sdi high, a rising edge on cnv initiates a conversion, selects cs mode, and forces sdo to high impedance. in this mode, cnv mus t be held high during the conversion phase and the subsequent data readback. (if sdi and cnv are low, sdo is driven low.) prior to the minimum conversion time, sdi can be used to select other spi devices, such as analog multi - plexers, but sdi must be ret urned high before the minimum conversion time elapses and then held high for the maximum possible conversion time to avoid the generatio n of the busy signal indicator. when the conversion is complete, the ad7985 enters the acquisition phase and powers dow n. each adc result can be read by bringing its sdi input low, which consequently outputs the msb onto sdo. the remaining data bits are then clocked by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used t o capture the data, a digital host using the sck falling edge allows a faster reading rate, provided that it has an acceptable hold time. after the 1 6 th sck falling edge, sdo returns to high impedance and another ad7985 can be read. ad7985 sdi sdo cnv sck convert data in clk digital host cs1 cs2 ad7985 sdi sdo cnv sck 07947-013 figure 30 . cs mode, 4 - wire without busy indicator connection diagram acquisition (n) acquisition (n ? 1) acquisition (n + 1) 1 2 begin data (n ? 1) conversion (n) end data (n ? 1) sck cnv sdo 14 15 conversion (n ? 1) end data (n ? 2) t conv t data 0 (i/o quiet time) (i/o quiet time) 16 14 15 16 1 15 14 13 2 0 1 2 sdi (i/o quiet time) t cyc t acq t quiet t sck t dis t dis t hsdo t hsdicnv t ssdicnv t en t en t dsdo t hsdo t data t conv 07947-014 figure 31 . cs mode, 4 - wire without busy indicator serial interface timing
ad7985 rev. a | page 22 of 28 cs mode, 4 - wire with busy indic ator this mode is usually used when a single ad7985 is connected to an spi - compatible digital host with an interrupt input and when it is desired to keep cnv, which is used to sample the analog input, independent of the signal used t o select the data reading. this independence is particularly important in applica - tions where low jitter on cnv is desired. this mode is available only in n ormal conversion mode ( turbo is low ). the connection diagram is shown in figure 32, and the corresponding timing is given in figure 33. with sdi high, a rising edge on cnv initiates a conversion, selects cs mode, and forces sdo to high impedan ce. in this mode, cnv must be held high during the conversion phase and the subsequent data readback. (if sdi and cnv are low, sdo is driven low.) prior to the minimum conversion time, sdi can be used to select other spi devices, such as analog multiplexe rs, but sdi must be returned low before the minimum conversion time elapses and then held low for the maximum possible conversion time to guarantee the generation of the busy signal indicator. when the conversion is complete, sdo goes from high imped - ance to low impedance. with a pull - up on the sdo line, this transition can be used as an interrupt signal to initiate the data readback controlled by the digital host. the ad7985 then enters the acquisition phase and powers down. the data bits are then clocked out, msb first, by subsequent sck falling edges. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate, provided that it has an accept - able hol d time. after the optional 1 7 th sck falling edge or when sdi go es high (whichever occurs first), sdo returns to high impedance. ad7985 sdi sdo cnv sck convert data in clk digital host irq vio 47k? cs1 turbo 07947-015 figure 32 . cs mode, 4 - wire with busy indicator connection diagram (i/o quiet time) sdo d15 d14 d1 d0 t dis t quiet sck 1 2 3 15 16 17 t sck t sckl t sckh t hsdo t dsdo t en conversion acquisition t conv t cyc t acq acquisition sdi cnv t ssdicnv t hsdicnv turbo = 0 07947-016 figure 33 . cs mode, 4 - wire with busy indicator serial interface timing
ad7985 rev. a | page 23 of 28 chain mode without b usy indicator this mode can be used to daisy - chain multiple ad7985 device s on a 3 - wire serial interface. it is available o nly in n ormal conversion mode ( turbo is low ). this feature is useful for reducing com - ponent count and wiring connections, for example, in isolated multiconverter applications or for systems with a limited inter - facing capacity. data readback is analogous to clocking a shift register. a connection diagram example using two ad7985 device s is shown in figure 34 , and the corresponding timing is given in figure 35. when sd i and cnv are low, sdo is driven low. with sck low, a rising edge on cnv initiates a conversion, selects chain mode, and disables the busy indicator. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when the con version is complete, the msb is output onto sdo , and the ad7985 enters the acquisition phase and powers down. the remaining data bits stored in the internal shift register are clocked by subsequent sck falling edges. for each adc, sdi feeds the input of th e internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb first, and 1 6 n clocks are required to read back the n adcs. the data is valid on both sck edges. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate and consequently more ad7985 device s in the chain, provided that the digital host has an acceptable hold time. the maximum conversion rate may be reduced due to the total rea dback time. convert data in clk digital host ad7985 sdi sdo cnv b sck ad7985 sdi sdo cnv a sck turbo turbo 07947-017 figure 34 . chain mode without busy indicator connection diagram turbo = 0 sdo a = sdi b d a 15 d a 14 d a 13 sck 1 2 3 30 31 32 t ssdisck t hsdisck t en conversion acquisition t conv t cyc t acq acquisition cnv d a 1 14 15 t sck t sckl t sckh d a 0 17 18 16 sdi a = 0 sdo b d b 15 d b 14 d b 13 d a 1 d b 1 d b 0 d a 15 d a 14 t hsdo t dsdo t quiet t hsckcnv d a 0 07947-018 figure 35 . chain mode without busy indicator serial interface timing
ad7985 rev. a | page 24 of 28 chain mode with busy indicator this mode can be us ed to daisy - chain multiple ad7985 device s on a 3 - wire serial interface while providing a busy indicator. it is available only in normal conversion mode (turbo is low). this feature is useful for reducing component count and wiring connections, for example , in isolated multiconverter applications or for systems with a limited interfacing capacity. data readback is analogous to clocking a shift register. a connection diagram example using three ad7985 device s is shown in figure 36 , and the corresponding timing is given in figure 37. when sdi and cnv are low, sdo is driven low. with sck high, a rising edge on cnv initiates a conversion, selects chain mode, and enables the busy indicator feature. in this mode, cnv is held high during the conversion phase and the subsequent data readback. when all adcs in the chain have completed their conversions, the sdo pin of the adc closest to the digital host (see the ad7985 adc labeled c i n figure 36 ) is driven high. this transition on sdo can be used as a busy indicator to trigger the data read - back controlled by the digital host. the ad7985 then enters the acquisition phase and powers down. the da ta bits stored in the internal shift register are clocked out, msb first, by subsequent sck falling edges. for each adc, sdi feeds the input of the internal shift register and is clocked by the sck falling edge. each adc in the chain outputs its data msb f irst, and 1 6 n + 1 clocks are required to read back the n adcs. although the rising edge can be used to capture the data, a digital host using the sck falling edge allows a faster reading rate and consequently more ad7985 device s in the chain, provided t hat the digital hos t has an acceptable hold time. convert data in clk digital host ad7985 sdi sdo cnv c sck ad7985 sdi sdo cnv a sck irq ad7985 sdi sdo cnv b sck turbo turbo turbo 07947-019 figure 36 . chain mode with busy indicator connection diagram sdo a = sdi b d a 15 d a 14 d a 13 sck 1 2 3 35 47 48 t en conversion acquisition t conv t cyc t acq acquisition cnv = sdi a d a 1 4 15 t sck t sckh t sckl d a 0 17 34 16 sdo b = sdi c d b 15 d b 14 d b 13 d a 1 d b 1 d b 0 d a 15 d a 14 49 t ssdisck t hsdisck t hsdo t dsdo sdo c d c 15 d c 14 d c 13 d a 1 d a 0 d c 1 d c 0 d a 14 19 31 32 18 33 d b 1 d b 0 d a 15 d b 15 d b 14 t dsdosdi t hsckcnv d a 0 t dsdosdi t dsdosdi t dsdosdi t dsdosdi turbo = 0 t ssckcnv 07947-020 figure 37 . chain mode with busy indicator serial interface timing
ad7985 rev. a | page 25 of 28 application s inform ation layout the printed circuit board (pcb) that houses the ad7985 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. the pinout of the ad7985 , with its analog signals on the left side a nd its digital signals on t he right side, eases this task. avoid running digital lines under the device because the y couple noise onto the die, unless a ground plane under the ad7985 is used as a shield. fast switching signals, such as cnv or clocks, shou ld not run near analog signal paths. crossover of digital and analog signals should be avoided. at least one ground plane should be used. it can be common or split between the digital and analog sections. in the latter case, the planes should be joined und erneath the ad7985 device s. the ad7985 voltage reference input s ( ref ) ha ve a dynamic input impedance and should be decoupled with minimal parasitic inductances. this is done by placing the reference decoupling ceramic capacitor close to, ideally right up a gainst, the ref and ref gnd pins and connecting them with wide, low impedance traces. finally, the power supplies , vdd and vio of the ad7985 , should be decoupled with ceramic capacitors, typically 100 nf, placed close to the ad7985 and connected using shor t, wide traces to provide low impedance paths and to reduce the effect of glitches on the power supply lines. evaluating ad7985 performance other recommended layouts for the ad7985 are outlined in the documentation for the ad7985 evaluation board ( e va l - ad7985 ebz ). the evaluation board package includes a fully assembled and tested evaluation board, documentation, and software for controlling the board from a pc via the e va l - ced 1 z board .
ad7985 rev. a | page 26 of 28 5 4 paddle 3 1 2 6 bvdd avdd dvdd vio gnd gnd gnd gnd gnd gnd gnd ref ref ref 07947-030 figure 38 . example layout of the ad79 85 (top layer) 5v external reference (adr435 or adr445) gnd vio c ref bvdd avdd dvdd vio gnd gnd gnd gnd gnd gnd gnd ref ref ref c bvdd c avdd c vio c dvdd 07947-031 figure 39 . example layout of the ad7985 (bottom layer)
ad7985 rev. a | page 27 of 28 outline dimensions 2.65 2.50 sq 2.35 3.75 bsc sq 4.00 bsc sq compliant to jedec standards mo-220-vggd-1 090408-b 1 0.50 bsc pin 1 indic a t or 0.50 0.40 0.30 t o p view 12 max 0.80 max 0.65 ty p sea ting plane pin 1 indic a t or coplanarit y 0.08 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 20 6 1 6 10 11 1 5 5 exposed pad (bottom view) 0.60 max 0.60 max 0.25 min for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 40 . 20 - lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp - 20 - 4) dimens ions shown in millimeters ordering guide model 1 , 2 , 3 temperature range package description package option ordering quantity ad798 5 bcpz ?40c to +85c 20- lead lead frame chip scale package [ lfcsp_vq ] , t ray cp -20-4 490 ad798 5 bcpz -rl7 ?40c to +85c 20- lead lead frame chip scale package [lfcsp_vq] , 7 tape and reel cp -20-4 1,500 eval - ad7985 e bz evaluation board eval - ced1z converter eva luation and development board 1 z = rohs compliant pa rt. 2 the eval - ad7985ebz can be used as a standalone evaluation board or in conjunction with the eval - ced1z for evaluation/demonstration purposes. 3 the eval - ced1z allows a pc to control and communicate with all analog devices evaluation boards ending in t h e eb designator.
ad7985 rev. a | page 28 of 28 notes ? 2009 - 2010 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d07947 - 0 - 8/10(a)

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